This invention relates to a phase-locked loop (PLL) for liquid crystal displays (LCDs) which generates a master clock signal synchronized with an external synchronous signal, and more particularly to a phase difference detector for preventing the phase difference variation due to an equalization signal.
In general, thin film transistor-liquid crystal displays (TFT-LCDs) generate a master clock signal synchronized with an external synchronous signal through a PLL. FIG. 1 shows a block diagram of the prior PLL circuit for generating a master clock signal in TFT-LCDs. The prior PLL circuit compares the phase between an external synchronous signal Csync and an internal synchronous signal Hsync from a synchronous signal generator 60 through a phase difference detector 10 to generate a phase difference detection signal PFD.
A voltage controlled oscillator (VCO) 30 varies its oscillation frequency according to the phase difference detection signal PFD to generate the master clock MCLK. A sampling clock signal generator 70 receives the master clock signal MCLK from the VCO 30 through a buffer 40 to generate sampling clock pulse CPH for sampling R, G and B data. Accordingly, the prior PLL circuit generates the master clock signal MCLK synchronized with the synchronous signal Csync as the VCO 30 varies the frequency of the master clock signal MCLK according to the phase difference detection signal PFD generated from the phase difference detector 10.
However, if a composite synchronous signal is received as the external synchronous signal, the equalization period is exist in a vertical synchronous signal. Because the equalization pulse having a 1/H period is exist in the equalization period, if the phase difference detector compares the phase between two synchronous signals, the frequency of the VCO 30 is abruptly varied by the excessive phase variation. Although in the vertical synchronous signal period video signals are not displayed, it takes a long time to completely stabilize the abrupt frequency variation in the equalization period, thereby affecting the early display of video signals. Accordingly, the distortion is occurred in the upper end of a screen.